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Ordering number : EN5213A
CMOS LSI
LC74725, 74725M
On-Screen Display Controller LSI
Overview
The LC74725 and LC74725M are built-in EDS on-screen display controller CMOS LSI products that display characters and patterns on a TV screen under microprocessor control. The characters displayed have an 8 x 8 dot format, and a dot interpolation function is provided. These LSIs can display ten lines of 24 characters each.
Package Dimensions
unit: mm 3067-DIP24S
[LC7425]
Features
* Display format: 24 characters by 10 lines (up to 240 characters) * Character format: 8 (horizontal) x 8 (vertical) dots (interpolation function provided) * Character sizes: Two horizontal and two vertical sizes * Characters in font: 64 characters * Initial display positions: 64 horizontal positions and 64 vertical positions * Blinking: Specifiable on a per-character basis * Blinking types: Two periods, 1.0 second and 0.5 second * Blue background screen display: Available in internal synchronization mode * External control input: 8-bit serial input format * Built-in sync separator circuit * EDS support * Video outputs: Composite video signal output in either NTSC or PAL-M * Package: 24-pin plastic DIP (300 mil) 24-pin plastic MFP (375 mil)
SANYO: DIP24S
3045B-MFP24
[LC7425M]
SANYO: MFP24
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
41096HA (OT)/O3195HA (OT) No. 5213-1/16
LC74725, 74725M Pin Assignment
Pin Functions
Pin No. 1 2 3 4 5 6 7 Symbol VSS1 XtalIN XtalOUT CTRL1 LN21 OSCIN OSCOUT Crystal oscillator input switching Data output LC oscillator Ground Crystal oscillator Function Description Ground connection (digital system ground) Connections for the external crystal and capacitors used to form a crystal oscillator for internal synchronizing signal generation. Alternatively, these pins can be used for external clock input (2fsc or 4fsc). Switches between external clock input mode and crystal oscillator mode. Low: crystal oscillator mode, high: external clock input mode. Line 21H pulse output (MOD0 = low: even field, MOD0 = high: both fields output) Connections for the external coil and capacitor used to form the character output dot clock generation oscillator. Outputs the judgment as to where there are or are not external synchronizing signals present. Outputs a high level when there are synchronizing signals. SEL0 = high: Outputs field discrimination pulses (O/E pulses) Outputs the dot clock (LC oscillator) when the CS1 pin is high and the RST pin is low. A command is provided that turns this output off. Outputs the crystal oscillator clock when the CS1 pin is low and the RST pin is low. A command is provided that turns this output off. Enable input for OSD serial data input. Serial data input is enabled when this pin is low. A pullup resistor is built in (hysteresis input). Serial data input clock input. A pull-up resistor is built in (hysteresis input). Serial data input. A pull-up resistor is built in (hysteresis input). Composite video signal level adjustment power supply (analog system power supply) Composite video signal output pin Must be either connected to ground or left open. Video signal input Power supply Sync separator circuit input Ground Composite synchronizing signal output Vertical synchronizing signal input Enable input Data output Reset input Power supply (+5 V) Composite video signal input pin Power supply (+5 V: digital system power supply) Video signal input to the built-in sync separator circuit Ground (digital system ground) Video signal output from the built-in sync separator circuit Inputs the vertical synchronizing signal generated by integrating the SEPOUT pin output signal. An integrating circuit must be inserted between the SEPOUT pin and this pin. This pin must be tied to VDD1 if unused. Enable input for EDS data output. EDS data output is enabled when this input is low. A pull-up resistor is built in (hysteresis input). EDS data output (either an n-channel open-drain or a CMOS output circuit) System reset input. A pull-up resistor is built in (hysteresis input). Power supply (+5 V: digital system power supply)
8
SYNCJDG
External synchronizing signal judgment output
9 10 11 12 13 14 15 16 17 18 19
CS1 SCLK SIN VDD2 CVOUT NC CVIN VDD1 SYNIN VSS1 SEPOUT SEPIN
Enable input Clock input Data input Power supply Video signal output
20
21 22 23 24
CS2 CPDT RST VDD1
Note: Both VDD1 pins must be connected to the power supply.
No. 5213-2/16
LC74725, 74725M
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max VOUT max Pd max Topr Tstg VDD1, VDD2 All input pins LN21, CPDT, SEPOUT, SYNCJDG Ta = 25C Conditions Ratings VSS - 0.3 to VSS + 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 350 -30 to +70 -40 to +125 Unit V V V mW C C
Allowable Operating Ranges at Ta = -30 to +70C
Parameter Supply voltage Symbol VDD1 VDD2 VIH1 VIH2 VIL1 VIL2 RPU VIN1 VIN2 VIN3 fOSC1 fOSC1 Oscillator frequency fOSC1 fOSC1 fOSC2 VDD1 VDD2 RST, CS1, CS2, SIN, SCLK CTRL1, SEPIN RST, CS1, CS2, SIN, SCLK CTRL1, SEPIN Applies to RST, CS1, CS2, SIN, SCLK, and the pins specified as options. CVIN: VDD1 = 5 V SYNIN: VDD1 = 5 V XtalIN (when external clock input is used), fIN = 2fsc or 4fsc: VDD1 = 5 V XtalIN, XtalOUT oscillator pins (2fsc: NTSC) XtalIN, XtalOUT oscillator pins (4fsc: NTSC) XtalIN, XtalOUT oscillator pins (2fsc: PAL-M) XtalIN, XtalOUT oscillator pins (4fsc: PAL-M) OSCIN, OSCOUT oscillator pins (LC oscillator) 5 1.5 0.1 7.159 14.318 7.151 14.302 12 Conditions min 4.5 4.5 0.8 VDD1 0.7 VDD1 VSS - 0.3 VSS - 0.3 25 50 2.0 2.0 2.5 5.0 typ 5.0 5.0 max 5.5 1.27 VDD1 VDD1 + 0.3 VDD1 + 0.3 0.2 VDD1 0.3 VDD1 90 Unit V V V V V V k Vp-p Vp-p Vp-p MHz MHz MHz MHz MHz
Input high level voltage
Input low level voltage
Pull-up resistance Composite video input voltage Input voltage
Note: Extreme care must be used to prevent noise when the XtalIN pin is used in clock input mode.
Electrical Characteristics at Ta = -30 to +70C, and unless otherwise specified, with VDD1 = 5 V
Parameter Input off leakage current Output off leakage current Output high level voltage Output low level voltage Input current Symbol Ileak1 Ileak2 VOH1 VOL1 IIH IIL IDD1 IDD2 VSN VPD VCBL VCBH VRSL VRSH CVIN CVOUT LN21, SYNCJDG, CPDT, SEPOUT: VDD1 = 4.5 V, IOH = -1.0 mA LN21, SYNCJDG, CPDT, SEPOUT: VDD1 = 4.5 V, IOL = 1.0 mA RST, CS1, CS2, SIN, SCLK, CTRL1, SEPIN: VIN = VDD1 CTRL1, OSCIN: VIN = VSS1 VDD1: All outputs open, crystal: 7.159 MHz, LC: 8 MHz VDD2: VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 0.69 0.89 1.28 1.47 0.97 1.16 1.60 1.79 1.44 1.63 1.96 2.16 0.81 1.01 1.40 1.59 1.09 1.28 1.72 1.91 1.56 1.75 2.08 2.28 -1 30 20 0.98 1.13 1.52 1.71 1.21 1.40 1.84 2.03 1.68 1.87 2.20 2.40 3.5 1.0 1 Conditions min typ max 1 1 Unit A A V V A A mA mA V V V V V V V V V V V V
Operating current drain
Sync level
Pedestal level
Color burst low level
Color burst high level
Background color low level
Background color high level
Continued on next page. No. 5213-3/16
LC74725, 74725M
Continued from preceding page.
Parameter Border level 0 Symbol VBK0 VBK1 VCHA Conditions When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V min 1.43 1.61 2.01 2.18 2.57 2.76 typ 1.55 1.73 2.13 2.30 2.69 2.88 max 1.67 1.85 2.25 2.42 2.81 3.00 Unit V V V V V V
Border level 1
Character level
Timing Characteristics at Ta = -30 to +70C, VDD1 = 5 V 0.5 V
Parameter OSD write (See Figure 1.) Minimum input pulse width tW (SCLK) tW (CS1) tSU (CS1) tSU (SIN) th (CS1) th (SIN) tword twt tCKCY Minimum input pulse width tCKL tCKH Data setup time Output delay time tICK tCKO SCLK CS1 (the period when CS1 is high) CS1 SIN CS1 SIN The time to write 8 bits of data The RAM data write time 200 1 200 200 2 200 4.2 1 ns s ns ns s ns s s Symbol Conditions min typ max Unit
Data setup time
Data hold time
One-word write time
ESD read (See Figure 2 for the n-channel open-drain circuit.) SCLK SCLK SCLK SCLK CPDT 2 1 1 10 0.5 ns s s s s
Note: Follows the OSD timing for the CMOS output circuit type.
Figure 1 OSD Serial Data Input Timing
No. 5213-4/16
LC74725, 74725M
Note: CPDT goes to the high-impedance state when CS2 is high.
Figure 2 EDS Serial Output Test Conditions (N-Channel Open-Drain Circuit)
Note: The O/E signal is output from the SYNCJDG pin when SEL0 is high. LN21 outputs the even field when MOD0 is low, and both fields when MOD0 is high.
Figure 3 O/E and LN21 Output Timing
No. 5213-5/16
LC74725, 74725M
Note: When closed caption character data is extracted in NTSC-TV mode (MOD0 is high), the control microprocessor can determine whether the current field is an odd field or an even field by checking the signal level output by the SYNCJDG pin (when SEL0 is high) at the point it detects the rise of the LN21 signal.
Figure 4 LC74725/M to Decoder LSI (or Microprocessor) Caption Data Transfer Technique 1 (This is the basic usage mode for these LSIs.)
Caption data transfer to the data output buffer is synchronized with the falling edge of the pulse output from LN21. Therefore, the following software processing is required if the decoder LSI (or microprocessor) does not detect the fall of LN21.
When MOD0 is low, since the data is output to the data buffer once (during the even field) in a single frame, the decoder LSI (or microprocessor) must perform the transfer control operation at least twice per frame (about 32 ms). When the transfer control operation is performed twice in the same frame, the second CPDT 16 bits of output data are all zeros. Therefore, the microprocessor must determine that the data for the next frame had not been transferred to the output buffer in this case. Note: The LC74725 hardware will not transfer data to the output buffer while CS2 is low. Therefore the decoder LSI (or microprocessor) must restore CS2 from the low level to the high level after completing a data transfer control cycle. This transfer technique (technique 2) cannot be used in NTSC-TV mode, i.e., when MOD0 is high.
Figure 5 LC74725/M to Decoder LSI (or Microprocessor) Caption Data Transfer Technique 2 (When a port to detect the fall of LN21 cannot be allocated in the decoder LSI (or Microprocessor).)
No. 5213-6/16
LC74725, 74725M System Block Diagram
No. 5213-7/16
LC74725, 74725M Display Control Commands Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. The following commands are supported. x y z { | } COMMAND0: Display memory (VRAM) write address setup command COMMAND1: Display character data write command COMMAND2: Vertical display start position and vertical character size setup command COMMAND3: Horizontal display start position and horizontal character size setup command COMMAND4: Display control setup command COMMAND5: Display control setup command
Display Control Command Table
First byte Command Command identification code 7 COMMAND0 Set write address COMMAND1 Write character COMMAND2 Set vertical display start position and vertical character size COMMAND3 Set horizontal display start position and horizontal character size COMMAND4 Display control COMMAND5 Synchronizing signal control 1 1 6 0 0 5 0 0 4 0 1 3 V3 0 2 V2 0 Data 1 V1 0 0 V0 0 7 0 at 6 0 0 5 0 c5 4 H4 c4 Second byte Data 3 H3 c3 2 H2 c2 1 H1 c1 0 H0 c0
1
0
1
0
0
VS 20 HS 20 RAM ERS PH
0
VS 10 HS 10 SYS RST INT
0
FS
VP 5 HP 5 NON 0
VP 4 HP 4 EG MUT
VP 3 HP 3 BK 1 MOD 0
VP 2 HP 2 BK 0 CTL 3
VP 1 HP 1 RV CTL 2
VP 0 HP 0 DSP ON SEL 0
1
0
1
1
EGP
0
0
LC
1 1
1 1
0 0
0 1
TST MOD BCL
OSC STP RSN
0 0
EGL 0
Once written, the command identification code in the first byte is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74725/M locks into the display character data write mode, and another first byte cannot be written. When a high level is input to the CS pin, the LC74725/M is set to COMMAND0 (display memory write address setup mode). x COMMAND0 (Display memory write address setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- V3 State 1 0 0 0 0 1 0 1 0 1 0 1 Display memory row address (0 to 9 hexadecimal) Command 0 identification code Set the display memory write address. Function Note
2
V2
1
V1
0
V0
No. 5213-8/16
LC74725, 74725M Second byte
Register content DA0 to DA7 7 6 5 4 Register name -- -- -- H4 State 0 0 0 0 1 0 1 0 1 0 1 0 1 Display memory column address (0 to 17 hexadecimal) Function Second byte identification bit Note
3
H3
2
H2
1
H1
0
H0
y COMMAND1 (Display character data write setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 2 1 0 Register name -- -- -- -- -- -- -- -- State 1 0 0 1 0 0 0 0 Command 1 identification code Set up display character data write. Function Note When this command is input, the LC74725/M locks into the display character data write mode until the CS1 pin goes high.
Second byte
Register content DA0 to DA7 7 6 5 Register name at -- c5 State 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 Character code (00 to 3F hexadecimal) Character attribute off Character attribute on Function Note
4
c4
3
c3
2
c2
1
c1
0
c0
No. 5213-9/16
LC74725, 74725M z COMMAND2 (Vertical display start position and vertical character size setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 2 1 0 Register name -- -- -- -- -- VS20 -- VS10 State 1 0 1 0 0 0 1 0 0 1 1H per dot 2H per dot First line vertical character size 1H per dot 2H per dot Second line vertical character size Command 2 identification code Set the vertical display start position and vertical character size. Function Note
Second byte
Register content DA0 to DA7 7 6 Register name -- FS VP5 (MSB) VP4 State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The vertical display start position is set by the 6 bits VP0 to VP5. The weight of bit 1 is 2H. Function Second byte identification bit Crystal oscillator frequency: 2fsc Crystal oscillator frequency: 4fsc If VS is the vertical display start position then: VS = H x (2 2nVPn) H: the horizontal synchronization pulse period
n=0 5
Note
5
4
3
VP3
2
VP2
1
VP1 VP0 (LSB)
0
{ COMMAND3 (Horizontal display start position and horizontal character size setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- EGP State 1 0 1 1 0 1 0 1 0 0 1 1 Tc per dot 2 Tc per dot First line horizontal character size Correction: off Correction: on 1 Tc per dot 2 Tc per dot Border specification when the horizontal double character size is used Second line horizontal character size Command 3 identification code Set the horizontal display start position and horizontal character size. Function Note
2 1 0
HS20 -- HS10
No. 5213-10/16
LC74725, 74725M Second byte
Register content DA0 to DA7 7 6 Register name -- LC HP5 (MSB) HP4 State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 If HS is the horizontal start position then: HS = Tc x (2 2nHPn)
n=0 5
Function Second byte identification bit An LC oscillator is used for the dot clock. A crystal oscillator is used for the dot clock.
Note
Selects the dot clock used in horizontal character display.
5
4
3
HP3
2
HP2
Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating mode.
The horizontal display start position is set by the 6 bits HP0 to HP5. The weight of bit 1 is 2Tc.
1
HP1 HP0 (LSB)
0
| COMMAND4 (Display control setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- TSTMOD State 1 1 0 0 0 1 0 1 0 1 0 1 Reset all registers and turn the display off. Erase display RAM (set to 3F hexadecimal) Do not stop the crystal oscillator and LC oscillator circuits. Stop the crystal oscillator and LC oscillator circuits. Normal operating mode Test mode This bit must be zero. The RAM erase operation requires about 500 s (It is executed in the DSPOFF state.) Valid when character display is off in external synchronization mode. Reset occurs when the CS1 pin is low, and the reset is cleared when CS1 goes high. Command 4 identification code Display control setup Function Note
2
RAMERS
1
OSCSTP
0
SYSRST
Second byte
Register content DA0 to DA7 7 6 Register name -- EGL State 0 0 1 0 1 0 1 0 1 0 2 BK0 1 1 RV 0 1 0 1 Blinking on Reverse (character reversing) off Reverse (character reversing) on Character display off Character display on Function Second byte identification bit Border level 0 (VBK0) Border level 1 (VBK1) Interlaced (262.5H per field) Noninterlaced (263H per field) Border off Border on Blinking period: about 0.5 s Blinking period: about 1.0 s Blinking off Switches the blinking period. When blinking is specified for reversed characters, the blinking will be between normal character and reversed character display. Switches the border level Switches between interlaced and noninterlaced Note
5
NON
4
EG
3
BK1
0
DSPON
No. 5213-11/16
LC74725, 74725M } COMMAND5 (Display control setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- BCL State 1 1 0 1 0 1 0 2 PH 1 0 1 RSN 1 0 INT 0 1 External synchronizing signal detection control: On External synchronization Internal synchronization Blue background External synchronizing signal detection control: Off Background color present No background color (only the background level is set) Green background Only valid in internal synchronization mode Background color switching (Only valid in NTSC mode) (In PAL-M mode, only blue is available as the background color.) External synchronizing signal detection control. Determines when the signal goes from detected to undetected, and from undetected to detected. Switches between external and internal synchronization Command 5 identification code Synchronizing signal control settings Function Note
Second byte
Register content DA0 to DA7 7 6 5 4 Register name -- -- -- MUT State 0 0 0 0 1 0 1 0 1 0 1 0 1 Normal output CVIN is cut and CVOUT is fixed at the pedestal level. Even field line 21 data extraction (VCR) Both even and odd field line 21 data extraction (NTSC-TV) Internal V separation used. Internal V separation not used. NTSC PAL-M External synchronizing signal detection output signal O/E signal Switches CVOUT. Switches line 21 data extraction operation. Switches V separation usage. Switches between generation of NTSC and PAL-M signals. Switches SYNCJDG (pin 21) output. Function Second byte identification bit Note
3
MOD0
2
CTL3
1
CTL2
0
SEL0
Note: The register states are all set to zero when the LC74725/M is reset with the RST pin.
No. 5213-12/16
LC74725, 74725M Display Screen Structure The display consists of 10 lines of 24 characters each and thus up to 240 characters can be displayed. Enlarging the size of the characters reduces the number of characters that can be displayed to under 240 characters. Display memory addresses are specified as row (0 to 9 decimal) and column (0 to 23 decimal) addresses. Display Screen Structure (display memory addresses)
No. 5213-13/16
LC74725, 74725M Composite Video Signal Output Level (internally generated level)
CVOUT Output Level Waveform (VDD2 = 5.00 V)
Output level VCHA: Character VRSH: Background color high VCBH: Color burst high VRSL: Background color low VBK1: Border VBK0: Border VPD: VSN: Pedestal VCBL: Color burst low Sync VDD2 = 5.00 V Output voltage [V] 2.69 2.08 1.72 1.56 2.13 1.55 1.40 1.09 0.81 Output voltage [V] 2.88 2.28 1.91 1.75 2.30 1.73 1.59 1.28 1.01
No. 5213-14/16
LC74725, 74725M Application Circuit Examples (Connected to a Y/C1 chip) 1. External system clock input
Note: Values listed are reference values.
No. 5213-15/16
LC74725, 74725M 2. Crystal oscillator clock generation
Note: Values listed are reference values.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5213-16/16

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